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set __TCLID "(Post-linking U280 XDMA Tcl hook): "

set __ip_list [get_property ip_repo_paths [current_project]]
lappend __ip_list ${CMAKE_SOURCE_DIR}/build/fpga-network-stack/iprepo
set_property ip_repo_paths $__ip_list [current_project]
update_ip_catalog

# *************************************************************************
puts "$${}{__TCLID}"

set __gt_k_list {}
set __gt_intf_width 0
# Make sure the kernel key in the config_info dict exists
if {[dict exists $config_info kernels]} {
  puts "$${}{__TCLID} got config_info"
  set __k_list [dict get $config_info kernels]
  # Make sure that list of kernels is populated  
  if {[llength $__k_list] > 0} {
    # Iterate over each kernel
    foreach __k_inst $__k_list {
      puts "$${}{__TCLID} K Inst: $${}{__k_inst}"
      set __cu_bd_cell_list [get_bd_cells -filter "VLNV=~*:*:$${}{__k_inst}:*"]
      #set __cu_bd_cell_list [get_bd_cells -quiet -filter "VLNV=~*:*:$${}{__k_inst}:*"]
      # Iterate over each compute unit for the current kernel
      foreach __cu_bd_cell $__cu_bd_cell_list {
        puts "$${}{__TCLID} CU Cell: $${}{__cu_bd_cell}"
        set __cu_bd_cell_sub [string range $__cu_bd_cell 1 [string length $__cu_bd_cell]]
        #Create a list of GT capable kernels. 
        set __gt_pins [get_bd_intf_pins -quiet -of_objects [get_bd_cells $__cu_bd_cell_sub] -filter {VLNV=~*gt_rtl*}]
        if {[llength $${}{__gt_pins} ] > 0} {
          puts "$${}{__TCLID} found gt interface on $__cu_bd_cell_sub"
          lappend __gt_k_list $__cu_bd_cell_sub
        }
      }
    }
  } else {
    puts "$${}{__TCLID} kernel list 0"
  }

  if {[llength $__gt_k_list] > 1} {
    puts "$${}{__TCLID} More than 1 GT interface is not supported. A single GT interface of max width 4 must be provided."
    exit
  }

  if {[llength $__gt_k_list] > 0} {
    puts "$${}{__TCLID} Iterating over kernels"

    puts "$${}{__TCLID} GT Kernel List $__gt_k_list"
    foreach __k_inst $__gt_k_list {
      set __gt_intf [get_bd_intf_pins -quiet -of_objects [get_bd_cells $__k_inst] -filter {VLNV=~*gt_rtl*}]
      if {[llength $__gt_intf] > 0} {
        puts "$${}{__TCLID} connecting GT"
        connect_bd_intf_net [get_bd_intf_ports io_gt_gtyquad_00] $__gt_intf
      }
      # Raw connection to "sub-nets" of clock bd_intf_port (as kernel cannot leave a clock bd_intf_pin hanging after
      # System Linker due to validate_bd_design)
      puts "$${}{__TCLID} TEMPORARY: Not connecting reference clock as diff clock due to post-System Linker validate error"
      set __refclk0_pins [get_bd_pins -of_objects [get_bd_cells $${}{__k_inst}] -filter {NAME =~ "gt_refclk0*"}]
      if {[llength $__refclk0_pins] > 0} {
        puts "$${}{__TCLID} connecting ref clk 0"
        connect_bd_net [get_bd_ports io_clk_gtyquad_refclk0_01_clk_n] [get_bd_pins $${}{__k_inst}/gt_refclk0_n]
        connect_bd_net [get_bd_ports io_clk_gtyquad_refclk0_01_clk_p] [get_bd_pins $${}{__k_inst}/gt_refclk0_p]
      }
      set __refclk1_pins [get_bd_pins -of_objects [get_bd_cells $${}{__k_inst}] -filter {NAME =~ "gt_refclk1*"}]
      if {[llength $__refclk1_pins] > 0} {
        puts "$${}{__TCLID} connecting ref clk 1"
        connect_bd_net [get_bd_ports io_clk_gtyquad_refclk1_01_clk_n] [get_bd_pins $${}{__k_inst}/gt_refclk1_n]
        connect_bd_net [get_bd_ports io_clk_gtyquad_refclk1_01_clk_p] [get_bd_pins $${}{__k_inst}/gt_refclk1_p]
      }
      set __freerunclk_pins [get_bd_pins -of_objects [get_bd_cells $${}{__k_inst}] -filter {NAME =~ "clk_gt_freerun"}]
      puts __freerunclk_pins
      if {[llength $__freerunclk_pins] ne 1} {
        puts "$${}{__TCLID} ERROR - No clk_gt_freerun pin found"
      } else {
        connect_bd_net [get_bd_ports clk_gt_freerun] [get_bd_pins $${}{__k_inst}/clk_gt_freerun]
      }
    }
  }
}
